192 lines
5.1 KiB
NASM
192 lines
5.1 KiB
NASM
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%include "startup-common.asm"
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startup_arch:
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cli
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; setting up Page Tables
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; Identity Mapping first GB
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mov ax, 0x7000
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mov es, ax
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xor edi, edi
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xor eax, eax
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mov ecx, 3 * 4096 / 4 ;PML4, PDP, PD / moves 4 Bytes at once
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cld
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rep stosd
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xor edi, edi
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;Link first PML4 to PDP
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mov DWORD [es:edi], 0x71000 | 1 << 1 | 1
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add edi, 0x1000
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;Link first PDP to PD
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mov DWORD [es:edi], 0x72000 | 1 << 1 | 1
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add edi, 0x1000
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;Link all PD's (512 per PDP, 2MB each)y
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mov ebx, 1 << 7 | 1 << 1 | 1
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mov ecx, 512
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.setpd:
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mov [es:edi], ebx
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add ebx, 0x200000
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add edi, 8
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loop .setpd
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xor ax, ax
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mov es, ax
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;cr3 holds pointer to PML4
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mov edi, 0x70000
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mov cr3, edi
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;enable Page Address Extension and Page Size Extension
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mov eax, cr4
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or eax, 1 << 5 | 1 << 4
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mov cr4, eax
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; load protected mode GDT
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lgdt [gdtr]
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mov ecx, 0xC0000080 ; Read from the EFER MSR.
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rdmsr
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or eax, 0x00000100 ; Set the Long-Mode-Enable bit.
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wrmsr
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;enabling paging and protection simultaneously
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mov ebx, cr0
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or ebx, 0x80000001 ;Bit 31: Paging, Bit 0: Protected Mode
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mov cr0, ebx
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; far jump to enable Long Mode and load CS with 64 bit segment
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jmp gdt.kernel_code:long_mode
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USE64
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long_mode:
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; load all the other segments with 64 bit data segments
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mov rax, gdt.kernel_data
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mov ds, rax
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mov es, rax
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mov fs, rax
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mov gs, rax
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mov ss, rax
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; load long mode IDT
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lidt [idtr]
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mov rsp, 0x800000 - 128
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mov rax, gdt.tss
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ltr ax
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;rust init
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mov eax, [kernel_base + 0x18]
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mov [interrupts.handler], rax
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mov rax, gdtr
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mov rbx, idtr
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mov rcx, tss
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int 0xFF
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.lp:
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sti
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hlt
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jmp .lp
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gdtr:
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dw gdt.end + 1 ; size
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dq gdt ; offset
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gdt:
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.null equ $ - gdt
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dq 0
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.kernel_code equ $ - gdt
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istruc GDTEntry
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at GDTEntry.limitl, dw 0
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at GDTEntry.basel, dw 0
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at GDTEntry.basem, db 0
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at GDTEntry.attribute, db attrib.present | attrib.user | attrib.code
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at GDTEntry.flags__limith, db flags.long_mode
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at GDTEntry.baseh, db 0
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iend
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.kernel_data equ $ - gdt
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istruc GDTEntry
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at GDTEntry.limitl, dw 0
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at GDTEntry.basel, dw 0
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at GDTEntry.basem, db 0
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; AMD System Programming Manual states that the writeable bit is ignored in long mode, but ss can not be set to this descriptor without it
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at GDTEntry.attribute, db attrib.present | attrib.user | attrib.writable
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at GDTEntry.flags__limith, db 0
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at GDTEntry.baseh, db 0
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iend
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.user_code equ $ - gdt
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istruc GDTEntry
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at GDTEntry.limitl, dw 0
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at GDTEntry.basel, dw 0
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at GDTEntry.basem, db 0
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at GDTEntry.attribute, db attrib.present | attrib.ring3 | attrib.user | attrib.code
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at GDTEntry.flags__limith, db flags.long_mode
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at GDTEntry.baseh, db 0
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iend
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.user_data equ $ - gdt
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istruc GDTEntry
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at GDTEntry.limitl, dw 0
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at GDTEntry.basel, dw 0
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at GDTEntry.basem, db 0
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; AMD System Programming Manual states that the writeable bit is ignored in long mode, but ss can not be set to this descriptor without it
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at GDTEntry.attribute, db attrib.present | attrib.ring3 | attrib.user | attrib.writable
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at GDTEntry.flags__limith, db 0
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at GDTEntry.baseh, db 0
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iend
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.user_tls equ $ - gdt
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istruc GDTEntry
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at GDTEntry.limitl, dw 0
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at GDTEntry.basel, dw 0
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at GDTEntry.basem, db 0
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; AMD System Programming Manual states that the writeable bit is ignored in long mode, but ss can not be set to this descriptor without it
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at GDTEntry.attribute, db attrib.present | attrib.ring3 | attrib.user | attrib.writable
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at GDTEntry.flags__limith, db 0
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at GDTEntry.baseh, db 0
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iend
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.tss equ $ - gdt
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istruc GDTEntry
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at GDTEntry.limitl, dw (tss.end - tss) & 0xFFFF
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at GDTEntry.basel, dw (tss-$$+0x7C00) & 0xFFFF
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at GDTEntry.basem, db ((tss-$$+0x7C00) >> 16) & 0xFF
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at GDTEntry.attribute, db attrib.present | attrib.ring3 | attrib.tssAvailabe64
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at GDTEntry.flags__limith, db ((tss.end - tss) >> 16) & 0xF
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at GDTEntry.baseh, db ((tss-$$+0x7C00) >> 24) & 0xFF
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iend
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dq 0 ;tss descriptors are extended to 16 Bytes
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.end equ $ - gdt
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struc TSS
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.reserved1 resd 1 ;The previous TSS - if we used hardware task switching this would form a linked list.
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.rsp0 resq 1 ;The stack pointer to load when we change to kernel mode.
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.rsp1 resq 1 ;everything below here is unused now..
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.rsp2 resq 1
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.reserved2 resd 1
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.reserved3 resd 1
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.ist1 resq 1
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.ist2 resq 1
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.ist3 resq 1
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.ist4 resq 1
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.ist5 resq 1
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.ist6 resq 1
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.ist7 resq 1
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.reserved4 resd 1
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.reserved5 resd 1
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.reserved6 resw 1
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.iomap_base resw 1
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endstruc
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tss:
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istruc TSS
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at TSS.rsp0, dd 0x800000 - 128
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at TSS.iomap_base, dw 0xFFFF
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iend
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.end:
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%include "interrupts-x86_64.asm"
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