156 lines
4.3 KiB
Rust
156 lines
4.3 KiB
Rust
use io::Mmio;
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#[repr(u8)]
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pub enum FisType {
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/// Register FIS - host to device
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RegH2D = 0x27,
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/// Register FIS - device to host
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RegD2H = 0x34,
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/// DMA activate FIS - device to host
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DmaAct = 0x39,
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/// DMA setup FIS - bidirectional
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DmaSetup = 0x41,
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/// Data FIS - bidirectional
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Data = 0x46,
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/// BIST activate FIS - bidirectional
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Bist = 0x58,
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/// PIO setup FIS - device to host
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PioSetup = 0x5F,
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/// Set device bits FIS - device to host
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DevBits = 0xA1
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}
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#[repr(packed)]
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pub struct FisRegH2D {
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// DWORD 0
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pub fis_type: Mmio<u8>, // FIS_TYPE_REG_H2D
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pub pm: Mmio<u8>, // Port multiplier, 1: Command, 0: Control
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pub command: Mmio<u8>, // Command register
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pub featurel: Mmio<u8>, // Feature register, 7:0
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// DWORD 1
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pub lba0: Mmio<u8>, // LBA low register, 7:0
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pub lba1: Mmio<u8>, // LBA mid register, 15:8
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pub lba2: Mmio<u8>, // LBA high register, 23:16
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pub device: Mmio<u8>, // Device register
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// DWORD 2
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pub lba3: Mmio<u8>, // LBA register, 31:24
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pub lba4: Mmio<u8>, // LBA register, 39:32
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pub lba5: Mmio<u8>, // LBA register, 47:40
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pub featureh: Mmio<u8>, // Feature register, 15:8
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// DWORD 3
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pub countl: Mmio<u8>, // Count register, 7:0
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pub counth: Mmio<u8>, // Count register, 15:8
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pub icc: Mmio<u8>, // Isochronous command completion
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pub control: Mmio<u8>, // Control register
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// DWORD 4
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pub rsv1: [Mmio<u8>; 4], // Reserved
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}
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#[repr(packed)]
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pub struct FisRegD2H {
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// DWORD 0
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pub fis_type: Mmio<u8>, // FIS_TYPE_REG_D2H
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pub pm: Mmio<u8>, // Port multiplier, Interrupt bit: 2
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pub status: Mmio<u8>, // Status register
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pub error: Mmio<u8>, // Error register
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// DWORD 1
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pub lba0: Mmio<u8>, // LBA low register, 7:0
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pub lba1: Mmio<u8>, // LBA mid register, 15:8
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pub lba2: Mmio<u8>, // LBA high register, 23:16
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pub device: Mmio<u8>, // Device register
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// DWORD 2
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pub lba3: Mmio<u8>, // LBA register, 31:24
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pub lba4: Mmio<u8>, // LBA register, 39:32
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pub lba5: Mmio<u8>, // LBA register, 47:40
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pub rsv2: Mmio<u8>, // Reserved
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// DWORD 3
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pub countl: Mmio<u8>, // Count register, 7:0
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pub counth: Mmio<u8>, // Count register, 15:8
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pub rsv3: [Mmio<u8>; 2], // Reserved
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// DWORD 4
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pub rsv4: [Mmio<u8>; 4], // Reserved
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}
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#[repr(packed)]
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pub struct FisData {
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// DWORD 0
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pub fis_type: Mmio<u8>, // FIS_TYPE_DATA
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pub pm: Mmio<u8>, // Port multiplier
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pub rsv1: [Mmio<u8>; 2], // Reserved
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// DWORD 1 ~ N
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pub data: [Mmio<u8>; 252], // Payload
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}
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#[repr(packed)]
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pub struct FisPioSetup {
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// DWORD 0
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pub fis_type: Mmio<u8>, // FIS_TYPE_PIO_SETUP
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pub pm: Mmio<u8>, // Port multiplier, direction: 4 - device to host, interrupt: 2
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pub status: Mmio<u8>, // Status register
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pub error: Mmio<u8>, // Error register
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// DWORD 1
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pub lba0: Mmio<u8>, // LBA low register, 7:0
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pub lba1: Mmio<u8>, // LBA mid register, 15:8
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pub lba2: Mmio<u8>, // LBA high register, 23:16
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pub device: Mmio<u8>, // Device register
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// DWORD 2
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pub lba3: Mmio<u8>, // LBA register, 31:24
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pub lba4: Mmio<u8>, // LBA register, 39:32
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pub lba5: Mmio<u8>, // LBA register, 47:40
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pub rsv2: Mmio<u8>, // Reserved
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// DWORD 3
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pub countl: Mmio<u8>, // Count register, 7:0
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pub counth: Mmio<u8>, // Count register, 15:8
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pub rsv3: Mmio<u8>, // Reserved
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pub e_status: Mmio<u8>, // New value of status register
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// DWORD 4
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pub tc: Mmio<u16>, // Transfer count
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pub rsv4: [Mmio<u8>; 2], // Reserved
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}
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#[repr(packed)]
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pub struct FisDmaSetup {
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// DWORD 0
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pub fis_type: Mmio<u8>, // FIS_TYPE_DMA_SETUP
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pub pm: Mmio<u8>, // Port multiplier, direction: 4 - device to host, interrupt: 2, auto-activate: 1
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pub rsv1: [Mmio<u8>; 2], // Reserved
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// DWORD 1&2
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pub dma_buffer_id: Mmio<u64>, /* DMA Buffer Identifier. Used to Identify DMA buffer in host memory. SATA Spec says host specific and not in Spec. Trying AHCI spec might work. */
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// DWORD 3
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pub rsv3: Mmio<u32>, // More reserved
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// DWORD 4
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pub dma_buffer_offset: Mmio<u32>, // Byte offset into buffer. First 2 bits must be 0
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// DWORD 5
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pub transfer_count: Mmio<u32>, // Number of bytes to transfer. Bit 0 must be 0
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// DWORD 6
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pub rsv6: Mmio<u32>, // Reserved
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}
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