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Add simple paging, use rust libcore and compile without sse

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This commit is contained in:
Jeremy Soller 2016-08-15 11:29:53 -06:00
commit 465363f0a1
18 changed files with 599 additions and 51 deletions
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61
arch/x86_64/src/main.rs
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@ -3,8 +3,20 @@
/// It must create the IDT with the correct entries, those entries are
/// defined in other files inside of the `arch` module
use super::idt::{IDTR, IDT, IDT_PRESENT, IDT_RING_0, IDT_INTERRUPT};
use super::mem::memset;
use externs::memset;
use idt;
use memory::{self, Frame};
use paging::{self, entry, PhysicalAddress};
/// Test of zero values in BSS.
static BSS_TEST_ZERO: usize = 0;
/// Test of non-zero values in BSS.
static BSS_TEST_NONZERO: usize = 0xFFFFFFFFFFFFFFFF;
extern {
/// Kernel main function
fn kmain() -> !;
}
extern {
/// The starting byte of the text (code) data segment.
@ -25,15 +37,6 @@ extern {
static mut __bss_end: u8;
}
/// Test of zero values in BSS.
static BSS_TEST_ZERO: usize = 0;
/// Test of non-zero values in BSS.
static BSS_TEST_NONZERO: usize = 0xFFFFFFFFFFFFFFFF;
extern {
fn kmain() -> !;
}
#[no_mangle]
pub unsafe extern fn kstart() -> ! {
asm!("xchg bx, bx" : : : : "intel", "volatile");
@ -52,21 +55,31 @@ pub unsafe extern fn kstart() -> ! {
debug_assert_eq!(BSS_TEST_NONZERO, 0xFFFFFFFFFFFFFFFF);
}
asm!("xchg bx, bx" : : : : "intel", "volatile");
// Set up IDT
idt::init(blank);
//Set up IDT
for entry in IDT.iter_mut() {
entry.set_flags(IDT_PRESENT | IDT_RING_0 | IDT_INTERRUPT);
entry.set_offset(8, blank as usize);
// Initialize memory management
let mut allocator = memory::init(0, &__bss_end as *const u8 as usize);
// Initialize paging
let mut pager = paging::init();
// Remap a section with `flags`
let mut remap_section = |start_ref: &u8, end_ref: &u8, flags: entry::EntryFlags| {
let start = start_ref as *const _ as usize;
let end = end_ref as *const _ as usize;
for i in 0..(start - end + paging::PAGE_SIZE - 1)/paging::PAGE_SIZE {
let frame = Frame::containing_address(PhysicalAddress::new(start + i * paging::PAGE_SIZE));
pager.identity_map(frame, flags, &mut allocator);
}
};
// Remap text read-only
{
asm!("xchg bx, bx" : : : : "intel", "volatile");
//TODO remap_section(& __text_start, & __text_end, entry::PRESENT);
}
IDTR.set_slice(&IDT);
IDTR.load();
asm!("xchg bx, bx" : : : : "intel", "volatile");
asm!("int 0xFF" : : : : "intel", "volatile");
asm!("xchg bx, bx" : : : : "intel", "volatile");
kmain();
}