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Orbital (#16)

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* Port previous ethernet scheme

* Add ipd

* Fix initfs rebuilds, use QEMU user networking addresses in ipd

* Add tcp/udp, netutils, dns, and network config

* Add fsync to network driver

* Add dns, router, subnet by default

* Fix e1000 driver. Make ethernet and IP non-blocking to avoid deadlocks

* Add orbital server, WIP

* Add futex

* Add orbutils and orbital

* Update libstd, orbutils, and orbital
Move ANSI key encoding to vesad

* Add orbital assets

* Update orbital

* Update to add login manager

* Add blocking primitives, block for most things except waitpid, update orbital

* Wait in waitpid and IRQ, improvements for other waits

* Fevent in root scheme

* WIP: Switch to using fevent

* Reorganize

* Event based e1000d driver

* Superuser-only access to some network schemes, display, and disk

* Superuser root and irq schemes

* Fix orbital
This commit is contained in:
Jeremy Soller 2016-10-13 17:21:42 -06:00 • committed by GitHub
parent 372d44f88c
commit 224c43f761
92 changed files with 3415 additions and 473 deletions
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26
drivers/ahcid/src/ahci/hba.rs
View file

@ -25,6 +25,10 @@ const HBA_SIG_ATAPI: u32 = 0xEB140101;
const HBA_SIG_PM: u32 = 0x96690101;
const HBA_SIG_SEMB: u32 = 0xC33C0101;
fn pause() {
unsafe { asm!("pause" : : : "memory" : "intel", "volatile"); }
}
#[derive(Debug)]
pub enum HbaPortType {
None,
@ -119,7 +123,9 @@ impl HbaPort {
cmdfis.counth.write(0);
}
while self.tfd.readf((ATA_DEV_BUSY | ATA_DEV_DRQ) as u32) {}
while self.tfd.readf((ATA_DEV_BUSY | ATA_DEV_DRQ) as u32) {
pause();
}
self.ci.writef(1 << slot, true);
@ -127,6 +133,7 @@ impl HbaPort {
if self.is.readf(HBA_PORT_IS_TFES) {
return None;
}
pause();
}
if self.is.readf(HBA_PORT_IS_TFES) {
@ -194,7 +201,9 @@ impl HbaPort {
}
pub fn start(&mut self) {
while self.cmd.readf(HBA_PORT_CMD_CR) {}
while self.cmd.readf(HBA_PORT_CMD_CR) {
pause();
}
self.cmd.writef(HBA_PORT_CMD_FRE, true);
self.cmd.writef(HBA_PORT_CMD_ST, true);
@ -203,7 +212,9 @@ impl HbaPort {
pub fn stop(&mut self) {
self.cmd.writef(HBA_PORT_CMD_ST, false);
while self.cmd.readf(HBA_PORT_CMD_FR | HBA_PORT_CMD_CR) {}
while self.cmd.readf(HBA_PORT_CMD_FR | HBA_PORT_CMD_CR) {
pause();
}
self.cmd.writef(HBA_PORT_CMD_FRE, false);
}
@ -267,7 +278,9 @@ impl HbaPort {
cmdfis.counth.write((sectors >> 8) as u8);
}
while self.tfd.readf((ATA_DEV_BUSY | ATA_DEV_DRQ) as u32) {}
while self.tfd.readf((ATA_DEV_BUSY | ATA_DEV_DRQ) as u32) {
pause();
}
self.ci.writef(1 << slot, true);
@ -276,6 +289,7 @@ impl HbaPort {
println!("IS_TFES set in CI loop TFS {:X} SERR {:X}", self.tfd.read(), self.serr.read());
return Err(Error::new(EIO));
}
pause();
}
if self.is.readf(HBA_PORT_IS_TFES) {
@ -312,7 +326,9 @@ pub struct HbaMem {
impl HbaMem {
pub fn reset(&mut self) {
self.ghc.writef(1, true);
while self.ghc.readf(1) {}
while self.ghc.readf(1) {
pause();
}
}
}