74 lines
2.5 KiB
Rust
74 lines
2.5 KiB
Rust
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#![feature(asm)]
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extern crate syscall;
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use syscall::iopl;
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use pci::{Pci, PciBar, PciClass};
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mod pci;
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fn enumerate_pci() {
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println!("PCI BS/DV/FN VEND:DEVI CL.SC.IN.RV");
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let pci = Pci::new();
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for bus in pci.buses() {
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for dev in bus.devs() {
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for func in dev.funcs() {
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if let Some(header) = func.header() {
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println!("PCI {:>02X}/{:>02X}/{:>02X} {:>04X}:{:>04X} {:>02X}.{:>02X}.{:>02X}.{:>02X} {:?}",
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bus.num, dev.num, func.num,
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header.vendor_id, header.device_id,
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header.class, header.subclass, header.interface, header.revision,
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PciClass::from(header.class));
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for i in 0..header.bars.len() {
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match PciBar::from(header.bars[i]) {
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PciBar::None => (),
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PciBar::Memory(address) => println!(" BAR {} {:>08X}", i, address),
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PciBar::Port(address) => println!(" BAR {} {:>04X}", i, address)
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}
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}
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match PciClass::from(header.class) {
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PciClass::Storage => match header.subclass {
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0x01 => {
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println!(" + IDE");
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},
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0x06 => {
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println!(" + SATA");
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},
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_ => ()
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},
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PciClass::SerialBus => match header.subclass {
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0x03 => match header.interface {
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0x00 => {
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println!(" + UHCI");
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},
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0x10 => {
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println!(" + OHCI");
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},
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0x20 => {
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println!(" + EHCI");
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},
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0x30 => {
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println!(" + XHCI");
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},
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_ => ()
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},
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_ => ()
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},
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_ => ()
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}
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}
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}
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}
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}
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}
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fn main() {
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unsafe { iopl(3).unwrap() };
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enumerate_pci();
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}
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