diff --git a/drivers/ahcid/src/ahci/hba.rs b/drivers/ahcid/src/ahci/hba.rs
index a5b3a13..3f6748c 100644
--- a/drivers/ahcid/src/ahci/hba.rs
+++ b/drivers/ahcid/src/ahci/hba.rs
@@ -78,6 +78,8 @@ impl HbaPort {
 
         self.clb.write(clb.physical() as u64);
         self.fb.write(fb.physical() as u64);
+        let is = self.is.read();
+        self.is.write(is);
 
         for i in 0..32 {
             let cmdheader = &mut clb[i];
@@ -272,11 +274,13 @@ impl HbaPort {
 
             while self.ci.readf(1 << slot) {
                 if self.is.readf(HBA_PORT_IS_TFES) {
+                    println!("IS_TFES set in CI loop TFS {:X} SERR {:X}", self.tfd.read(), self.serr.read());
                     return Err(Error::new(EIO));
                 }
             }
 
             if self.is.readf(HBA_PORT_IS_TFES) {
+                println!("IS_TFES set after CI loop TFS {:X} SERR {:X}", self.tfd.read(), self.serr.read());
                 return Err(Error::new(EIO));
             }
 
@@ -306,6 +310,13 @@ pub struct HbaMem {
     pub ports: [HbaPort; 32], // 0x100 - 0x10FF, Port control registers
 }
 
+impl HbaMem {
+    pub fn reset(&mut self) {
+        self.ghc.writef(1, true);
+        while self.ghc.readf(1) {}
+    }
+}
+
 #[repr(packed)]
 pub struct HbaPrdtEntry {
     dba: Mmio<u64>, // Data base address