417 lines
14 KiB
Rust
417 lines
14 KiB
Rust
use std::mem::size_of;
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use std::ops::DerefMut;
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use std::{ptr, u32};
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use dma::Dma;
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use io::{Io, Mmio};
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use syscall::error::{Error, Result, EIO};
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use super::fis::{FisType, FisRegH2D};
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const ATA_CMD_READ_DMA_EXT: u8 = 0x25;
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const ATA_CMD_WRITE_DMA_EXT: u8 = 0x35;
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const ATA_CMD_IDENTIFY: u8 = 0xEC;
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const ATA_DEV_BUSY: u8 = 0x80;
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const ATA_DEV_DRQ: u8 = 0x08;
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const HBA_PORT_CMD_CR: u32 = 1 << 15;
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const HBA_PORT_CMD_FR: u32 = 1 << 14;
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const HBA_PORT_CMD_FRE: u32 = 1 << 4;
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const HBA_PORT_CMD_ST: u32 = 1;
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const HBA_PORT_IS_ERR: u32 = 1 << 30 | 1 << 29 | 1 << 28 | 1 << 27;
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const HBA_SSTS_PRESENT: u32 = 0x3;
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const HBA_SIG_ATA: u32 = 0x00000101;
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const HBA_SIG_ATAPI: u32 = 0xEB140101;
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const HBA_SIG_PM: u32 = 0x96690101;
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const HBA_SIG_SEMB: u32 = 0xC33C0101;
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fn pause() {
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unsafe { asm!("pause" : : : "memory" : "intel", "volatile"); }
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}
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#[derive(Debug)]
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pub enum HbaPortType {
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None,
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Unknown(u32),
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SATA,
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SATAPI,
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PM,
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SEMB,
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}
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#[repr(packed)]
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pub struct HbaPort {
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pub clb: [Mmio<u32>; 2], // 0x00, command list base address, 1K-byte aligned
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pub fb: [Mmio<u32>; 2], // 0x08, FIS base address, 256-byte aligned
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pub is: Mmio<u32>, // 0x10, interrupt status
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pub ie: Mmio<u32>, // 0x14, interrupt enable
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pub cmd: Mmio<u32>, // 0x18, command and status
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pub _rsv0: Mmio<u32>, // 0x1C, Reserved
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pub tfd: Mmio<u32>, // 0x20, task file data
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pub sig: Mmio<u32>, // 0x24, signature
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pub ssts: Mmio<u32>, // 0x28, SATA status (SCR0:SStatus)
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pub sctl: Mmio<u32>, // 0x2C, SATA control (SCR2:SControl)
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pub serr: Mmio<u32>, // 0x30, SATA error (SCR1:SError)
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pub sact: Mmio<u32>, // 0x34, SATA active (SCR3:SActive)
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pub ci: Mmio<u32>, // 0x38, command issue
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pub sntf: Mmio<u32>, // 0x3C, SATA notification (SCR4:SNotification)
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pub fbs: Mmio<u32>, // 0x40, FIS-based switch control
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pub _rsv1: [Mmio<u32>; 11], // 0x44 ~ 0x6F, Reserved
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pub vendor: [Mmio<u32>; 4], // 0x70 ~ 0x7F, vendor specific
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}
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impl HbaPort {
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pub fn probe(&self) -> HbaPortType {
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if self.ssts.readf(HBA_SSTS_PRESENT) {
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let sig = self.sig.read();
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match sig {
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HBA_SIG_ATA => HbaPortType::SATA,
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HBA_SIG_ATAPI => HbaPortType::SATAPI,
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HBA_SIG_PM => HbaPortType::PM,
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HBA_SIG_SEMB => HbaPortType::SEMB,
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_ => HbaPortType::Unknown(sig),
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}
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} else {
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HbaPortType::None
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}
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}
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pub fn start(&mut self) {
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while self.cmd.readf(HBA_PORT_CMD_CR) {
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pause();
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}
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self.cmd.writef(HBA_PORT_CMD_FRE | HBA_PORT_CMD_ST, true);
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}
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pub fn stop(&mut self) {
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self.cmd.writef(HBA_PORT_CMD_ST, false);
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while self.cmd.readf(HBA_PORT_CMD_FR | HBA_PORT_CMD_CR) {
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pause();
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}
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self.cmd.writef(HBA_PORT_CMD_FRE, false);
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}
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pub fn slot(&self) -> Option<u32> {
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let slots = self.sact.read() | self.ci.read();
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for i in 0..32 {
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if slots & 1 << i == 0 {
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return Some(i);
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}
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}
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None
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}
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pub fn init(&mut self, clb: &mut Dma<[HbaCmdHeader; 32]>, ctbas: &mut [Dma<HbaCmdTable>; 32], fb: &mut Dma<[u8; 256]>) {
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self.stop();
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for i in 0..32 {
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let cmdheader = &mut clb[i];
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cmdheader.ctba.write(ctbas[i].physical() as u64);
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cmdheader.prdtl.write(0);
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}
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self.clb[0].write(clb.physical() as u32);
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self.clb[1].write((clb.physical() >> 32) as u32);
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self.fb[0].write(fb.physical() as u32);
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self.fb[1].write((fb.physical() >> 32) as u32);
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let is = self.is.read();
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self.is.write(is);
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self.ie.write(0);
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let serr = self.serr.read();
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self.serr.write(serr);
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// Disable power management
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let sctl = self.sctl.read() ;
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self.sctl.write(sctl | 7 << 8);
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// Power on and spin up device
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self.cmd.writef(1 << 2 | 1 << 1, true);
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print!("{}", format!(" - AHCI init {:X}\n", self.cmd.read()));
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}
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pub unsafe fn identify(&mut self, clb: &mut Dma<[HbaCmdHeader; 32]>, ctbas: &mut [Dma<HbaCmdTable>; 32]) -> Option<u64> {
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self.is.write(u32::MAX);
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let dest: Dma<[u16; 256]> = Dma::new([0; 256]).unwrap();
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if let Some(slot) = self.slot() {
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let cmdheader = &mut clb[slot as usize];
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cmdheader.cfl.write(((size_of::<FisRegH2D>() / size_of::<u32>()) as u8));
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cmdheader.prdtl.write(1);
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{
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let cmdtbl = &mut ctbas[slot as usize];
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ptr::write_bytes(cmdtbl.deref_mut() as *mut HbaCmdTable as *mut u8, 0, size_of::<HbaCmdTable>());
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let prdt_entry = &mut cmdtbl.prdt_entry[0];
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prdt_entry.dba.write(dest.physical() as u64);
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prdt_entry.dbc.write(512 | 1);
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}
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{
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let cmdfis = &mut *(ctbas[slot as usize].cfis.as_mut_ptr() as *mut FisRegH2D);
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cmdfis.fis_type.write(FisType::RegH2D as u8);
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cmdfis.pm.write(1 << 7);
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cmdfis.command.write(ATA_CMD_IDENTIFY);
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cmdfis.device.write(0);
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cmdfis.countl.write(1);
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cmdfis.counth.write(0);
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}
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while self.tfd.readf((ATA_DEV_BUSY | ATA_DEV_DRQ) as u32) {
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pause();
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}
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self.ci.writef(1 << slot, true);
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self.start();
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while (self.ci.readf(1 << slot) || self.tfd.readf(0x80)) && self.is.read() & HBA_PORT_IS_ERR == 0 {
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pause();
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}
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self.stop();
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if self.is.read() & HBA_PORT_IS_ERR != 0 {
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print!("{}", format!("ERROR IS {:X} TFD {:X} SERR {:X}\n", self.is.read(), self.tfd.read(), self.serr.read()));
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return None;
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}
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let mut serial = String::new();
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for word in 10..20 {
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let d = dest[word];
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let a = ((d >> 8) as u8) as char;
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if a != '\0' {
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serial.push(a);
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}
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let b = (d as u8) as char;
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if b != '\0' {
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serial.push(b);
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}
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}
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let mut firmware = String::new();
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for word in 23..27 {
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let d = dest[word];
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let a = ((d >> 8) as u8) as char;
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if a != '\0' {
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firmware.push(a);
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}
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let b = (d as u8) as char;
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if b != '\0' {
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firmware.push(b);
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}
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}
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let mut model = String::new();
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for word in 27..47 {
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let d = dest[word];
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let a = ((d >> 8) as u8) as char;
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if a != '\0' {
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model.push(a);
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}
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let b = (d as u8) as char;
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if b != '\0' {
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model.push(b);
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}
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}
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let mut sectors = (dest[100] as u64) |
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((dest[101] as u64) << 16) |
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((dest[102] as u64) << 32) |
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((dest[103] as u64) << 48);
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let lba_bits = if sectors == 0 {
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sectors = (dest[60] as u64) | ((dest[61] as u64) << 16);
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28
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} else {
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48
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};
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print!("{}", format!(" + Serial: {} Firmware: {} Model: {} {}-bit LBA Size: {} MB\n",
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serial.trim(), firmware.trim(), model.trim(), lba_bits, sectors / 2048));
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Some(sectors * 512)
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} else {
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None
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}
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}
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pub fn ata_dma(&mut self, block: u64, sectors: usize, write: bool, clb: &mut Dma<[HbaCmdHeader; 32]>, ctbas: &mut [Dma<HbaCmdTable>; 32], buf: &mut Dma<[u8; 256 * 512]>) -> Result<usize> {
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if write {
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//print!("{}", format!("AHCI {:X} DMA BLOCK: {:X} SECTORS: {} WRITE: {}\n", (self as *mut HbaPort) as usize, block, sectors, write));
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}
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assert!(sectors > 0 && sectors < 256);
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self.is.write(u32::MAX);
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if let Some(slot) = self.slot() {
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if write {
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//print!("{}", format!("SLOT {}\n", slot));
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}
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let cmdheader = &mut clb[slot as usize];
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cmdheader.cfl.write(((size_of::<FisRegH2D>() / size_of::<u32>()) as u8) | if write { 1 << 7 | 1 << 6 } else { 0 });
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cmdheader.prdtl.write(1);
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{
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let cmdtbl = &mut ctbas[slot as usize];
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unsafe { ptr::write_bytes(cmdtbl.deref_mut() as *mut HbaCmdTable as *mut u8, 0, size_of::<HbaCmdTable>()) };
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let prdt_entry = &mut cmdtbl.prdt_entry[0];
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prdt_entry.dba.write(buf.physical() as u64);
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prdt_entry.dbc.write(((sectors * 512) as u32) | 1);
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}
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{
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let cmdfis = unsafe { &mut *(ctbas[slot as usize].cfis.as_mut_ptr() as *mut FisRegH2D) };
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cmdfis.fis_type.write(FisType::RegH2D as u8);
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cmdfis.pm.write(1 << 7);
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if write {
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cmdfis.command.write(ATA_CMD_WRITE_DMA_EXT);
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} else {
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cmdfis.command.write(ATA_CMD_READ_DMA_EXT);
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}
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cmdfis.lba0.write(block as u8);
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cmdfis.lba1.write((block >> 8) as u8);
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cmdfis.lba2.write((block >> 16) as u8);
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cmdfis.device.write(1 << 6);
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cmdfis.lba3.write((block >> 24) as u8);
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cmdfis.lba4.write((block >> 32) as u8);
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cmdfis.lba5.write((block >> 40) as u8);
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cmdfis.countl.write(sectors as u8);
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cmdfis.counth.write((sectors >> 8) as u8);
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}
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if write {
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//print!("WAIT ATA_DEV_BUSY | ATA_DEV_DRQ\n");
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}
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while self.tfd.readf((ATA_DEV_BUSY | ATA_DEV_DRQ) as u32) {
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pause();
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}
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if write {
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//print!("{}", format!("WRITE CI {:X} in {:X}\n", 1 << slot, self.ci.read()));
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}
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self.ci.writef(1 << slot, true);
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self.start();
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if write {
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//print!("{}", format!("WAIT CI {:X} in {:X}\n", 1 << slot, self.ci.read()));
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}
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while (self.ci.readf(1 << slot) || self.tfd.readf(0x80)) && self.is.read() & HBA_PORT_IS_ERR == 0 {
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pause();
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if write {
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//print!("{}", format!("WAIT CI {:X} TFD {:X} IS {:X} CMD {:X} SERR {:X}\n", self.ci.read(), self.tfd.read(), self.is.read(), self.cmd.read(), self.serr.read()));
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}
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}
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self.stop();
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if self.is.read() & HBA_PORT_IS_ERR != 0 {
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print!("{}", format!("ERROR IS {:X} IE {:X} CMD {:X} TFD {:X}\nSSTS {:X} SCTL {:X} SERR {:X} SACT {:X}\nCI {:X} SNTF {:X} FBS {:X}\n",
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self.is.read(), self.ie.read(), self.cmd.read(), self.tfd.read(),
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self.ssts.read(), self.sctl.read(), self.serr.read(), self.sact.read(),
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self.ci.read(), self.sntf.read(), self.fbs.read()));
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self.is.write(u32::MAX);
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return Err(Error::new(EIO));
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}
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if write {
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//print!("{}", format!("SUCCESS {}\n", sectors));
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}
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Ok(sectors * 512)
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} else {
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print!("No Command Slots\n");
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Err(Error::new(EIO))
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}
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}
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}
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#[repr(packed)]
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pub struct HbaMem {
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pub cap: Mmio<u32>, // 0x00, Host capability
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pub ghc: Mmio<u32>, // 0x04, Global host control
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pub is: Mmio<u32>, // 0x08, Interrupt status
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pub pi: Mmio<u32>, // 0x0C, Port implemented
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pub vs: Mmio<u32>, // 0x10, Version
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pub ccc_ctl: Mmio<u32>, // 0x14, Command completion coalescing control
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pub ccc_pts: Mmio<u32>, // 0x18, Command completion coalescing ports
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pub em_loc: Mmio<u32>, // 0x1C, Enclosure management location
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pub em_ctl: Mmio<u32>, // 0x20, Enclosure management control
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pub cap2: Mmio<u32>, // 0x24, Host capabilities extended
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pub bohc: Mmio<u32>, // 0x28, BIOS/OS handoff control and status
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pub _rsv: [Mmio<u8>; 116], // 0x2C - 0x9F, Reserved
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pub vendor: [Mmio<u8>; 96], // 0xA0 - 0xFF, Vendor specific registers
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pub ports: [HbaPort; 32], // 0x100 - 0x10FF, Port control registers
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}
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impl HbaMem {
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pub fn init(&mut self) {
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/*
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self.ghc.writef(1, true);
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while self.ghc.readf(1) {
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pause();
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}
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*/
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self.ghc.write(1 << 31 | 1 << 1);
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print!("{}", format!(" - AHCI CAP {:X} GHC {:X} IS {:X} PI {:X} VS {:X} CAP2 {:X} BOHC {:X}",
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self.cap.read(), self.ghc.read(), self.is.read(), self.pi.read(),
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self.vs.read(), self.cap2.read(), self.bohc.read()));
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}
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}
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#[repr(packed)]
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pub struct HbaPrdtEntry {
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dba: Mmio<u64>, // Data base address
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_rsv0: Mmio<u32>, // Reserved
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dbc: Mmio<u32>, // Byte count, 4M max, interrupt = 1
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}
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#[repr(packed)]
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pub struct HbaCmdTable {
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// 0x00
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cfis: [Mmio<u8>; 64], // Command FIS
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// 0x40
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acmd: [Mmio<u8>; 16], // ATAPI command, 12 or 16 bytes
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// 0x50
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_rsv: [Mmio<u8>; 48], // Reserved
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// 0x80
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prdt_entry: [HbaPrdtEntry; 65536], // Physical region descriptor table entries, 0 ~ 65535
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}
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#[repr(packed)]
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pub struct HbaCmdHeader {
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// DW0
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cfl: Mmio<u8>, /* Command FIS length in DWORDS, 2 ~ 16, atapi: 4, write - host to device: 2, prefetchable: 1 */
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pm: Mmio<u8>, // Reset - 0x80, bist: 0x40, clear busy on ok: 0x20, port multiplier
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prdtl: Mmio<u16>, // Physical region descriptor table length in entries
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// DW1
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prdbc: Mmio<u32>, // Physical region descriptor byte count transferred
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// DW2, 3
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ctba: Mmio<u64>, // Command table descriptor base address
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// DW4 - 7
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_rsv1: [Mmio<u32>; 4], // Reserved
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}
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